As is known, in a memory device employing a floating gate n-channel MOS (NMOS) transistor as an elementary cell, the possibility to modulate the threshold voltage of the NMOS elementary cell is used to discriminate between two logic states.
The virgin state of the memory cell, characterized by absence of charge from the floating gate of the transistor, is conventionally taken to represent a first logic state, or logic "1", while the programmed state of the cell is taken to represent a second logic state, or logic "0". In particular, the programmed state is characterized by the number of electrons in the floating gate being sufficient to produce a substantial rise in the threshold voltage of the cell.
During a reading phase, the memory cell is biased with a gate-source voltage which equals the supply voltage to the memory device, with the source terminal being brought to a ground value and the drain terminal to a value of about 1V.
If the cell has been written, its threshold voltage is higher than the supply voltage, and no current will flow through it. In a dual way, if the cell has been erased, its threshold voltage should be such that a current can flow through it.
In the instance of a memory device, specifically of the FLASH type, organized into a matrix of rows and columns of cells, the memory column containing the cell of interest is connected to a read voltage reference, and the current flowing through that column is sensed by a specially provided sense amplifier. Sensing the current flow through the memory column allows written cells to be discriminated from erased cells.
The range of threshold voltage values of a plurality of memory cells following electric erasing lies typically between 0.5V and 2.5V. To ensure proper reading from the memory device, this range is to comply with suitable design specifications.
Specifically, the bottom limit of this range is set to ensure that there are no depleted cells (i.e., cells with a threshold voltage below zero), and to avoid damaging the thin oxide while the memory cell is being read, the top limit being tied to the inherent width of the range, in turn related to the manufacturing process.
With a read voltage that is normally the same as the supply value, supply voltages above 3V pose no problems. Problems are encountered at low supply voltages, typically of about 2.5V, when erased memory cells with threshold voltages close to the top limit of the above range drain insufficient current, and are read as written memory cells.
A widely employed solution to the problem of false readings comprises a row decoding circuit which applies a boosted read voltage to an addressed memory row containing a memory cell to be read.
A higher read voltage than the supply voltage is thus delivered to the memory cells to be read, while retaining the threshold voltage ranges of the erased cells. This boosted read voltage is usually generated from a booster circuit.
Several embodiments of the booster circuit are currently available which are based on the above principle.
1) Continuous Boost
In this first embodiment, suitable clock pulses are delivered to the booster circuit from a clock circuit, whenever a reading phase is to be carried out, which charge a boost capacitor included in the booster circuit, thereby raising an output read voltage from the booster circuit to a value above the supply voltage. The boost capacitor will then hold the read voltage at a desired boosted value.
This first known embodiment allows small boost capacitors to be used, since the boosted read voltage is generated in a series of small increments. Due to the same way of operating, however, the time taken to initially charge the boost capacitor is fairly long, resulting in increased access time for the power-up phase, or reversion from power-down, and for the reversion from standby phase.
In particular, to reduce the delay for reversion from standby, a second, smaller size booster circuit may be used conventionally which holds the main boost capacitor charged even in the standby mode. But the introduction of the second booster circuit has a drawback in that the memory device as a whole is caused to consume power even in the standby mode. Current specifications for memory devices require instead that no power be consumed in the standby mode.
2) Global Pulsed Boost
This second embodiment provides for the use of a very large size boost capacitor. Boosted is, in fact, the whole row decoding circuitry.
The boost capacitor is charged (boost phase) by a single pulse at a predetermined time, e.g., on the occurrence of a switch signal for the reading phase or for the enabling phase of the memory device (e.g., for reversion from the standby phase).
This second embodiment does solve the problems of access time for the power-up and reversion from standby phase, without involving unnecessary power consumption. However, the provision of a large size boost capacitor with its drive circuits requires more area for the memory device as a whole.
In addition, this second known embodiment introduces new problems related to the timing of the capacitor boost phase.
3) Local Pulsed Boost
In this third embodiment, the boost phase is only used when actually needed, so that the advantages of the first and second embodiments above can be retained.
A row decoding circuit 1 based on this principle is shown diagrammatically in FIG. 1 and described in detail in European Patent Application No. 96830345.3, filed on Jun. 18, 1996 by this Applicant.
The row decoding circuit 1 with local pulsed boost is connected between a supply voltage reference Vcc and a ground potential reference GND, and has first 2 and second 3 control terminals, and first 4 and second 5 input terminals.
In particular, the first input terminal 4 receives an n-th row enable signal P1 for a memory device connected to the row decoding circuit 1, while the second input terminal 5 receives an (n+1)-th row enable signal P2. The enable signals P1 and P2 are mutually exclusive.
The first control terminal 2 receives a general enable signal CONTROL and is connected to the gate terminal of a control transistor M5, in turn connected between the supply voltage reference Vcc and a node X to be boosted. The second control terminal 3 receives a drive signal Vgc.
The control transistor M5 is a P-channel MOS (PMOS) transistor having its body terminal connected to its drain terminal, in turn connected to the second control terminal 3 through an n-th row decoding final inverter 6 and an (n+1)-th row decoding final inverter 8.
The node X to be boosted is further connected to one end of a boost capacitor Cboost having the other end connected to the supply voltage reference Vcc through a limitation circuit 10 which comprises, in particular, a PMOS transistor M6 in a diode configuration, having its body terminal connected to its drain terminal and to the boost capacitor Cboost.
The row decoding final inverters 6 and 8 of the circuit 1 are CMOS inverters comprising complementary NMOS/PMOS transistor pairs. The operation of these final inverters is controlled by turning on and off respective enable PMOS transistors M3 and M2 thereof.
The n-th row decoding final inverter 6 has a first central connection terminal Y1 connected to an n-th row equivalent impedance block 11, and a second central connection terminal of a row decoding final inverter 7 which has another central connection terminal connected to the first input terminal 4.
The (n+1)-th row decoding final inverter 8 similarly has a first central connection terminal Y3 connected to an (n+1)-th row equivalent impedance block, and a second central connection terminal Y4 connected to a central connection terminal of a row decoding final inverter 9 having, in turn, another central connection terminal connected to the second input terminal 5.
The row decoding final inverters 7 and 9 of the circuit 1 also are CMOS inverters comprising complementary NMOS/PMOS transistor pairs, and their operation is controlled by turning on and off respective enable PMOS transistors M1 and M4 thereof.
Let us see now the operation of the row decoding circuit 1 with local pulsed boost, according to the prior art.
The general enable signal CONTROL controls the `off` state of the control transistor M5, the transistor being adapted to power the row decoding final inverters 6 and 8 of the circuit 1. In particular, the signal CONTROL should turn off M5 before the arrival of the boost pulse, not to dissipate the charge stored in the boost capacitor Cboost.
The limitation circuit 10, and specifically the limitation transistor M6 thereof, is formed in the proximity of the remote end of the boost capacitor Cboost from the node X to be boosted, such that any excess charge in the boost capacitor Cboost can be dissipated through said transistor M6 and the voltage at the node X to be boosted cannot exceed a limitation value LIM equal to the sum of the supply voltage Vcc plus the threshold voltage Vtp of the PMOS transistor M6.
This is an essential condition to the operation of the row decoding circuit 1 because, upon the voltage at the node X to be boosted exceeding the above limitation value LIM, all the row decoding final inverters, i.e., the inverters 6 and 8 in the example of FIG. 1, might be turned on. In fact, for the row decoding circuit to operate properly, only the inverter of the selected row should be `on`, and all the others left `off`.
To obtain a memory configuration wherein the n-th row is "high" (P1=Vcc) and the (n+1)-th row grounded (P2=0), as exemplified in FIG. 1, the row decoding circuit 1 must ensure that the enable transistor M3 of the n-th row decoding final inverter 6 is `on` and the enable transistor M2 of the (n+1)-th row decoding final inverter 8 is `off`.
As can be appreciated from the schematics of FIG. 1, the enable transistor M2 is driven from the control transistor M4, being supplied the voltage Vcc, and accordingly, has its gate terminal at Vcc; therefore, the transistor M2 is held `off` so long as its source terminal, corresponding to the node X to be boosted, is at a voltage value below the limitation value LIM.
This leads back to the essential condition for proper operation of the row decoding circuit 1: the boost voltage Vboost at the node X to be boosted, as provided by the boost capacitor Cboost, should be limited to the sum of the supply voltage Vcc plus the threshold voltage of a PMOS transistor, of the same type of those employed in the final inverters, in an effective manner, and its operation should be clocked without in any way affecting the other functions of the row decoding circuit 1.
The advantages and disadvantages of conventional row decoding circuits are summarized in the following Table:
TABLE I ______________________________________ Boost Type Advantages Disadvantages ______________________________________ Continuous Boost Compact. Power consumption in Good performance. standby mode. Delays in the reversion from standby. Global Pulsed No delays in the Space requirements difficult Boost reversion from standby. to manage. No power consumption in standby mode. Local Pulsed No delays in the Limited boost voltage Boost reversion from standby. Vboost No power consumption in standby mode. Pulse is more easily generated. ______________________________________
Thus, the third local pulse boosted embodiment retains the advantages of the first two embodiments, i.e., near zero delay in reverting from the standby mode and no power consumption while in that mode. On the other hand, it has a shortcoming in that it can only be used for limited boost voltages Vboost.
This is disadvantageous especially where the memory device connected to the row decoding circuit is operated on low supply voltages. The use of low supply voltages has become a necessity in the field of integrated circuits mainly on account of a demand for low power consumption which is most pressing where the application concerns portable devices, such as cellular phones.
The integrated circuits currently employed in cellular phone applications must be designed for operation on supply voltages within the range of 2.7 to 3.6V, a range that would have to be even wider at the integrated circuit testing stage to ensure its proper operation under different real conditions.
Furthermore, a current market trend favors a shift of that operating range to 1.8V. Thus, the whole circuitry is to be re-designed for operation within this new voltage range.
Whereas for a minimum value of 2.5V of the supply voltage, the proper operation of the row decoding circuit is ensured by a limitation value LIM of the boost voltage Vboost equal to the supply voltage and by a threshold voltage of a PMOS transistor (equal to 0.8V, for example), a minimum value of 1.8V requires that the boost voltage Vboost be increased.